NXP Semiconductors /LPC408x_7x /MCPWM /CON

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Interpret as CON

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (STOP_)RUN0 0 (EDGE_ALIGNED_)CENTER0 0 (PASSIVE_STATE_IS_LOW)POLA0 0 (DEAD_TIME_DISABLED_)DTE0 0 (UPDATE)DISUP0 0RESERVED 0 (STOP_)RUN1 0 (EDGE_ALIGNED_)CENTER1 0 (PASSIVE_STATE_IS_LOW)POLA1 0 (DEAD_TIME_DISABLED_)DTE1 0 (UPDATE)DISUP1 0RESERVED 0 (STOP_)RUN2 0 (EDGE_ALIGNED_)CENTER2 0 (PASSIVE_STATE_IS_LOW)POLA2 0 (DEAD_TIME_DISABLED_)DTE2 0 (UPDATE)DISUP2 0RESERVED0 (OPPOSITE)INVBDC 0 (3_PHASE_AC_MODE_OFF)ACMODE 0 (3_PHASE_DC_MODE_OFF)DCMODE

INVBDC=OPPOSITE, DCMODE=3_PHASE_DC_MODE_OFF, DTE2=DEAD_TIME_DISABLED_, RUN0=STOP_, DTE0=DEAD_TIME_DISABLED_, DISUP0=UPDATE, POLA2=PASSIVE_STATE_IS_LOW, ACMODE=3_PHASE_AC_MODE_OFF, POLA0=PASSIVE_STATE_IS_LOW, DISUP1=UPDATE, POLA1=PASSIVE_STATE_IS_LOW, CENTER1=EDGE_ALIGNED_, RUN1=STOP_, DTE1=DEAD_TIME_DISABLED_, CENTER2=EDGE_ALIGNED_, RUN2=STOP_, CENTER0=EDGE_ALIGNED_, DISUP2=UPDATE

Description

PWM Control read address

Fields

RUN0

Stops/starts timer channel 0.

0 (STOP_): Stop.

1 (RUN_): Run.

CENTER0

Edge/center aligned operation for channel 0.

0 (EDGE_ALIGNED_): Edge-aligned.

1 (CENTER_ALIGNED_): Center-aligned.

POLA0

Selects polarity of the MCOA0 and MCOB0 pins.

0 (PASSIVE_STATE_IS_LOW): Passive state is LOW, active state is HIGH.

1 (PASSIVE_STATE_IS_HIG): Passive state is HIGH, active state is LOW.

DTE0

Controls the dead-time feature for channel 0.

0 (DEAD_TIME_DISABLED_): Dead-time disabled.

1 (DEAD_TIME_ENABLED_): Dead-time enabled.

DISUP0

Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).

0 (UPDATE): Functional registers are updated from the write registers at the end of each PWM cycle.

1 (NOUPDATE): Functional registers remain the same as long as the timer is running.

RESERVED

Reserved.

RUN1

Stops/starts timer channel 1.

0 (STOP_): Stop.

1 (RUN_): Run.

CENTER1

Edge/center aligned operation for channel 1.

0 (EDGE_ALIGNED_): Edge-aligned.

1 (CENTER_ALIGNED_): Center-aligned.

POLA1

Selects polarity of the MCOA1 and MCOB1 pins.

0 (PASSIVE_STATE_IS_LOW): Passive state is LOW, active state is HIGH.

1 (PASSIVE_STATE_IS_HIG): Passive state is HIGH, active state is LOW.

DTE1

Controls the dead-time feature for channel 1.

0 (DEAD_TIME_DISABLED_): Dead-time disabled.

1 (DEAD_TIME_ENABLED_): Dead-time enabled.

DISUP1

Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).

0 (UPDATE): Functional registers are updated from the write registers at the end of each PWM cycle.

1 (NOUPDATE): Functional registers remain the same as long as the timer is running.

RESERVED

Reserved.

RUN2

Stops/starts timer channel 2.

0 (STOP_): Stop.

1 (RUN_): Run.

CENTER2

Edge/center aligned operation for channel 2.

0 (EDGE_ALIGNED_): Edge-aligned.

1 (CENTER_ALIGNED_): Center-aligned.

POLA2

Selects polarity of the MCOA2 and MCOB2 pins.

0 (PASSIVE_STATE_IS_LOW): Passive state is LOW, active state is HIGH.

1 (PASSIVE_STATE_IS_HIG): Passive state is HIGH, active state is LOW.

DTE2

Controls the dead-time feature for channel 1.

0 (DEAD_TIME_DISABLED_): Dead-time disabled.

1 (DEAD_TIME_ENABLED_): Dead-time enabled.

DISUP2

Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).

0 (UPDATE): Functional registers are updated from the write registers at the end of each PWM cycle.

1 (NOUPDATE): Functional registers remain the same as long as the timer is running.

RESERVED

Reserved.

INVBDC

Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.

0 (OPPOSITE): The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time).

1 (SAME): The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)

ACMODE

3-phase AC mode select (see Section 24.8.7).

0 (3_PHASE_AC_MODE_OFF): 3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register.

1 (3_PHASE_AC_MODE_ON_): 3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0.

DCMODE

3-phase DC mode select (see Section 24.8.6).

0 (3_PHASE_DC_MODE_OFF): 3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)

1 (3_PHASE_DC_MODE_ON_): 3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs.

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